On Fri, 18 May 2001, Matt Waters wrote: > Anyway, I digress. As for "efficient use of data", what I meant by > that was that since the data bus allows the processor to process > 64-bit chunks at a time as opposed to 32-bit chunks, the cpu can > handle more data in a given instant. Basically, I was commenting on > the wider bus. Hold up. What I'm getting at is that *moving* data, which is what the bus does, is not connected to *processing* the data. You can hang a 1024-bit bus off a chip, but if it has 16-bit registers, then it still can only process 16-bits at a time. So I still ask if you're talking about bus width or register width. The thing with having a wide data bus is that you won't have the computer sitting around waiting for cycles to pass while the memory arrives, if you do it right. But this is getting into splitting hairs between system throughput and *processor* throughput, which is one component of the former. > BTW, if any of you know much about the mips and say that the data bus is > only 32 bits wide, and it's the registers that are 64 bits big, please let > me know. Well, think about that for a second. I have a hard time seeing how you'd benefit from needing two fetch instructions to load up a register... A peek at MIPS web site should tell you for sure. -- "To misattribute a quote is unforgivable." --Anonymous